The applicant claims and requests a foreign priority, through the Paris Convention for the Protection of Industry Property, based on a patent application filed in the Republic of Korea (South Korea) with the filing date of Aug. 14, 2000, with the patent application number 2000-0046852, by the applicant. (See the Attached Declaration)
1. Field of the Invention
The present invention relates to an asynchronous controller generation method, and more particularly, to a process-oriented asynchronous controller generation method in which an asynchronous controller is divided into a process controller and a process sequencing controller on the basis of a process corresponding to a node on a data flow graph.
2. Description of the Related Art
As an ultra-high speed and low power consumption system is rapidly spread and increasingly required, a system design trends based on an asynchronous method. In particular, an asynchronous system has a little clock skew, low power consumption, a high performance and a low electromagnetic interference in comparison with those of a synchronous system.
In the conventional art, an asynchronous control circuit generation is classified into a centralized control circuit generation method and a hardware-oriented control circuit generation method.
FIG. 1 is a block diagram showing an asynchronous controller of a conventional centralized controller generation method.
The whole system of FIG. 1 includes an input/output processing part 20 having an input selector 21, a register 22 and an output selector 23, a data processor 30 including adders, subtracters and multipliers for performing various operations and a controller 10. The conventional centralized controller generation method includes only one integrated controller 10 with respect to the whole system, which method is typically used in the design of a control circuit with respect to a synchronous system, which operates in synchronization with global clock. In the case of the centralized controller generation method, all control signals should be generated from the controller 10 and the size of the controller 10 is generally large. Thus, in the case that the above controller design method is applied to an asynchronous controller, many pieces of information concerning jobs and job sequence to be performed in a system is integrated in a single controller, to thereby cause a complicated specification. In this case, the asynchronous controller of the centralized controller generation method without having global clock cannot realize a large-scale asynchronous controller without reduction in a parallel performance, increase in a circuitry area, increase in a synthesis time at the time of performing a synthesis with an existing asynchronous logic synthesis program, and any hazard.
FIG. 2 is a block diagram showing an asynchronous controller of a conventional hardware-oriented controller generation method.
The asynchronous controller 40 of a conventional hardware-oriented controller generation method of FIG. 2 employs a controller design method contrived for an asynchronous system in which the controller 40 is divided into a number of control circuits CP1xcx9cCPn on the basis of hardware constituting the system in order to solve the problems generated in the asynchronous controller of the centralized controller generation method. In this method, the designer can divide the whole control circuit on the basis of the construction module of the circuit, and thus is more effective at the time of designing a small-scale system. However, in the case that the number of the hardware components is limited in relation with the circuit area, the asynchronous controller of the conventional hardware-oriented controller generation method also has problems of reduction of performance, increase in the area and synthesis time rapidly in the same way as those of the controller of the centralized controller generation method.
To solve the above problems, it is an object of the present invention to provide a process-oriented asynchronous controller generation method having an excellent area, performance and synthesis time, in which an asynchronous controller is divided and induced into a number of process controllers for generating control signals necessary for performing a process corresponding to a node on a data flow graph and a process sequencing controller for controlling a performance sequence of each process controller from the data flow graph.
To accomplish the above object of the present invention, there is provided a method for generating an asynchronous controller for forming a signal transition graph representing a state of change in input/output signals of the asynchronous controller from a data flow graph showing a performance sequence between a plurality of nodes each representing a process and a plurality of processes, and controlling a data processor to perform an operation from the signal transition graph by a logic synthesis program, the asynchronous controller generation method comprising: a process controller formation step of forming a signal transition graph of a plurality of process controllers for outputting control signals necessary for executing a process corresponding to a node in the data flow graph; a process sequencing controller formation step of forming a signal transition graph of a process sequencing controller according to a performance sequence of the process controllers from the data flow graph; and a logic synthesis step of generating an asynchronous controller in a logic synthesis program, by using the state of change in the input/output signals on the signal transition graph of the process controllers formed in the process controller formation step and the state of change in the input/output signals on the signal transition graph of the process sequencing controller formed in the process sequencing controller formation step.
According to another aspect of the present invention, there is also provided a method for generating an asynchronous controller for forming a finite state machine including an input burst which is a set of input signals of the asynchronous controller and an output burst which is a set of output signals corresponding to the input signals from a data flow graph showing a performance sequence between a plurality of nodes each representing a process and a plurality of processes, and controlling a data processor to perform an operation from the finite state machine by a logic synthesis program, the asynchronous controller generation method comprising: a process controller formation step of forming a finite state machine including an input burst being a set of input signals input to a process controller and an output burst being a set of output signals output from the process controller in order to output control signals necessary for executing a process corresponding to a node in the data flow graph; a process sequencing controller formation step of forming a finite state machine of a process sequencing controller according to a performance sequence of the process controllers from the data flow graph; and a logic synthesis step of generating an asynchronous controller in a logic synthesis program, by using the state of change in the input burst and the output burst of the finite state machine in the process controllers formed in the process controller formation step and the state of change in the input burst and the output burst in the finite state machine of the process sequencing controller formed in the process sequencing controller formation step.